Over the recent years a growing interest has been seen in the area of highly sensitive semiconductor devices that can be used for charge detection in liquids (e.g. ion sensitive field-effect transistor (ISFET)-type for hydrogen ions, as applied in the determination of pH-concentrations, detection of biomolecules, studies of DNA replication and genome sequences, etc.), or for the detection of ions or polarisable molecules in gaseous mixtures. Hybrid forms of such semiconductor devices have previously been proposed and demonstrated (S-R. Chang et al. Sensors 9, 2009, pp. 8336-8348 and H. Yuan et al. Biosensors and Bioelectronics 28, 2011, pp. 434-437), Ref. 1-2. These hybrids combine in a single integrated circuit an ISFET charge-sensitive device in parallel with a lateral bipolar junction transistor (LBJT). Such hybrid devices beneficially combine the high sensitivity of the ISFET with the additional amplification provided by the LBJT.
The term “ISFET” employed herein includes various equivalent forms of such devices (P. Bergveld, Sensors and Actuators B 88, 2003, pp. 1-20), see also Ref. 3-6. For example, the conductive gate electrode may be of metal or other suitable conductive material such as highly doped polycrystalline silicon. Similarly, the gate insulating material may be an oxide, such as silicon dioxide, but may as well comprise oxynitride or even high-k dielectrics.
Arrangements are known where the gate-electrode is brought in contact with the gas or liquid to be analysed via a consecutive arrangement of contacts/metal-lines and vias/metal-lines encapsulated by suitable passivation materials, as for example silicon oxide, silicon nitride or a sandwich of oxide/nitride. The metal film in the electrode in closest proximity to the liquid or gas may or may not be enclosed by said passivation. The metal itself may be a standard metal used in the manufacturing of semiconductor devices, such as aluminium, palladium, platinum or gold. The electrode may alternatively be in some form of metal/metal-oxide (Al2O3, Ta2O5, HfO2).
Disclosed in U.S. Pat. No. 8,283,736 is an ion sensing device constituting an ISFET connected to a lateral bipolar device integrated on same semiconductor chip. As disclosed, a p-channel ISFET, is located in an n-well with a lateral pnp bipolar transistor connected in parallel with emitter/source and drain/collector, respectively, in common and with a separate base connection. When an appropriate amount of ions are accumulated (or depleted) at the gate electrode, as a result of bias applied to the reference electrode immersed in the electrolyte, the channel conduction in the ISFET is altered. That, in turn, affects the conduction of the lateral bipolar device.
A drawback of this particular architecture is the parallel arrangement of the two devices, which requires an additional terminal. To this comes the inherently low gain of the gated lateral bipolar transistor. At a bias lower than the turn-on voltage of the bipolar device, the sub-threshold characteristics resemble those of the metal-oxide-semiconductor field-effect transistor (MOSFET) device, i.e. ISFET in this context. The transconductance enhancement obtained in the hybrid configuration primarily occurs above the threshold voltage of the MOSFET. As a consequence, the amplification of this structure will be very low.
The parasitic vertical pnp-transistor indicated in the referenced patent, is common to all n-well based CMOS processes. It is formed by the source/emitter of the ISFET, the externally connected n-well base with the p-type substrate as collector. It is not part of the sensing device, since a conductivity change in the ISFET does not influence said parasitic component. Active use of the parasitic vertical pnp-transistor could eventually cause reliability problems, e.g. latch-up. A further concern is the requirement of additional terminals for external connection of the individual devices in the desired configuration. Such additional wiring is likely to introduce unwanted signal noise.
U.S. Pat. No. 5,126,806 describes a lateral insulated gate bipolar transistor (IGBT), which is particularly well suited for high power switching applications. Disclosed is an enhancement-MOSFET device having its source and drain electrodes connected to the base and emitter, respectively, of a lateral bipolar transistor. When an appropriate gate input voltage, here in the form of a positive charge, is applied to the MOSFET, the channel conducts, thus biasing the bipolar transistor into conduction. The applied charge on the gate electrode can be used to control a large current through the bipolar device, which is of particular interest in power applications. Safe switching operation at high voltages, however, requires a very wide base and a low gain in the bipolar transistor. Various forms of said devices have been integrated in modern CMOS processes as described by Bakeroot et al. in IEEE EDL-28, pp. 416-418, 2007, Ref. 7. Relevant in this context is also a report by E. Kho Ching Tee entitled “A review of techniques used in Lateral Insulated Gate Bipolar Transistor (LIGBT)” in Journal of Electrical and Electronics Engineering, vol. 3, pp. 35-52, 2012, Ref. 8. While this type of device is potentially quite useful for various forms of power switching, with its requirements of high voltage capability and low internal gain, it is disadvantageous for a device incorporated in a circuit intended for charge detection (of particularly hydrogen ions) in liquids or gaseous mixtures.
A prior-art ISFET-gated LBJT is described with reference to FIGS. 1A and 1B. Referring first to FIG. 1A, there is depicted a side view of the prior art device 10 representative of a device disclosed in the above cited U.S. Pat. No. 8,283,736. As shown in the Figure, the gated LBJT 10 is constructed by forming an n-well 12 in a p-type substrate 11, forming p+-doped regions in the n-well 12 and forming a lateral collector ring 15 around an emitter 13 in the p+-doped regions, respectively.
The gated LBJT 10 has an enclosed gate electrode 18, between p+-doped regions, on top of a gate dielectric layer 17. In addition, a base contact 14 is formed in an n+-doped region in the n-well 12. Likewise, a p+-doped region 16, outside the n-well is provided as substrate contact.
The gate electrode 18 and the p+-doped regions on adjacent sides, which function as source/drain contacts, constitute a p-type MOSFET device.
The floating gate electrode 18 is electrically connected by a plurality of contacts/vias and metal layers 21 to a hydrogen ion sensing electrode 19 above the gated LBJT. The surface of the sensing electrode 19 is in contact with an ion-containing solution 22 to which a reference gate-electrode 20 is attached.
In the prior art of FIG. 1A, the MOSFET drain region and the bipolar transistor collector region are inherently connected because they are formed from the same p+-conductivity type semiconductor region.
The MOSFET source region and the bipolar emitter region are likewise connected since they are formed by the same p+-type semiconductor region 13. In the particular structure depicted in FIG. 1A, an n+-region 14 is made in the n-well 12 for a common external bias connection to the base region of the bipolar lateral and vertical pnp transistors as well as to the body of the p-type MOSFET (ISFET).
Referring now to FIG. 1B, which is the equivalent circuit for the device in FIG. 1A, it can be seen that there are four terminals; B 14, C 15, E 13, S 16 in addition to that of the external reference gate-electrode, Ref 20. It can be seen that the p-type MOSFET has its source 13 and drain 15 terminals connected in parallel to the emitter (E) and collector (C) of the lateral bipolar device 5. It is similarly observed that both the lateral pnp-transistor and the vertical (parasitic) pnp-transistor 6 share emitter (E) and base (B) terminals.
Applying proper bias to the source/drain terminals of the MOSFET and to the reference electrode will result in a lateral current in the MOSFET device.
Forward biasing of the emitter-base junction will add a lateral current, which is picked up by the lateral collector ring (15) in FIG. 1A and will also add a vertical substrate current that will be globally distributed in the substrate (11) in FIG. 1A.
Any change in the reference potential will affect both the MOSFET current as well as the current passing through the bipolar device(s).
For the described prior art device, any change of potential or charge in the electrolyte part is primarily sensed by the parallel arrangement 5 of the MOSFET transistor and the lateral pnp-bipolar transistor.
The fact that the active layers are shared between the p-type MOSFET and the lateral pnp-transistor, respectively, leads to a non-optimised low current-gain pnp-transistor.
In addition, the substrate current from the vertical parasitic pnp-transistor 6 is disadvantageous from a device isolation point and does not provide information with respect to changes in the electrolyte part.
FIG. 2A shows one example of prior art in the form of LIGBT such as described in U.S. Pat. No. 5,126,806 mentioned above. The integrated device 30 is constructed in a low-doped n-type layer 35 containing a p-type doped region 50 with a higher impurity concentration than that of the n-type layer and a p+ region 70 with an impurity concentration exceeding that of the p-type doped region 50. In the p-doped region 50 is provided an n+-region 60 with an impurity concentration that is higher than that of the p-type region 50. The p-doped region 50 and the n+-region 60 are electrically short-circuited by an emitter electrode 55. A collector electrode 65 forms an ohmic contact to the p+-region 70. An insulating film serves as gate dielectric 40 and separates the gate electrode 45 from the substrate.
When a positive potential is applied to the gate electrode 45, the conductivity of a surface portion of the p-region 50 under the gate dielectric 40 is inverted to form an n-type channel. Electrons from the n+-region 60 can then pass through the channel, into the n− layer 35 and on to the p+-region 70 from which positive holes are injected. Thereby the n− layer 35, having a high resistivity, is conductivity-modulated to provide a low resistance path between the anode (C) and cathode (E) in FIG. 2A. A low on-resistance and excellent forward blocking characteristic can thus be realised, which is quite useful for various forms of power switching.
Numerous modifications of the above described embodiment, with emphasis on improved switching performance, exist, some of which are covered in a report by E. Kho Ching Tee, Ref. 8.
FIG. 2B, is an equivalent electrical circuit diagram for the device in FIG. 2A. Shown are the three terminals, C, E and G. The device also utilises an external back-side substrate electrode. The n-type MOSFET has its source and body terminals strapped together at (E) and these are, in turn, connected to the collector region (C) of the lateral bipolar pnp-transistor over the body resistance, R1. Shown is also how the base terminal of the lateral pnp-transistor is connected to the drain of the MOSFET over a variable resistance, R2, the latter mirroring the conductivity modulation.
A vertical parasitic npn-transistor that has its base connected to the collector of the lateral pnp-transistor is included in FIG. 2B to illustrate that the LIGBT contains a thyristor-like structure. Once this thyristor causes latch-up, the LIGBT device can no longer be controlled by the gate potential. The condition for latch-up is: αnpn+αpnp≥1, where αnpn and αpnp are the common-base current gains of the parasitic npn transistor and pnp transistor, respectively. To reduce the risk for latch-up, it is essential to lower the current gain α in both transistors. Since the pnp transistor carries the on-state voltage drop, the gain of the npn-transistor has to be suppressed by, e.g., increasing the base doping below the emitter region (lowering the base resistance).